A Hardware Architecture Design Of Motion Compensation Decoder For AVS

AVS is digital audio/video coding standard which is established by the Audio Video Coding Stand Working Group of China(AVS working group in short). As for the coding efficiency, the coding efficiency of AVS is equal with H.264/AVC, however, the former is as two times better than that of MPEG-2. Therefore, the computational complexity of AVS is greatly large than that of MPEG-2. Furthermore, for some real-time applications, the complicated computational characteristics will lead to great challenges for today's hardware implementation. In this paper, we propose a hardware architecture design of AVS motion compensation decoder.Briefly introduction of development of video compression standards and the key techniques is presented in this paper. Besides, the technical characteristics of AVS and its profiles and levels are introduced in detail.In order to achieve the computation-efficient system architecture, with the help of RISC model, the system complexity is thoroughly explored, which is composed of computationl complexity and spatial complexity. Meanwhile, in order to meet the requirement of system, we propose three different optimization models, setting quarter-pixel interpolation module as an example.Based on the design complexity exploration of AVS system, the architecture model of motion compensation decoding system of AVS is proposed. According to the decoding algorithms of AVS, the system architecture is composed of three major computing units: motion vecter generation unit, prediction unit and reconstruction unit. By using Global and independent Local Memory methodology, the data path is simplified.A hardware architecture design for motion vector generation algorithm in AVS is proposed in this paper. This architecture give attention to motion vector generation for both temporal conjoint block mode and spatial conjoint block one. Furthermore, two motion vector buffers are designed to reduce data response between bus data and this module.A specific parallel architecture design for the quarter-pixel interpolation is proposed in this paper. This proposed process architecture can calculate different position pixels according to different configuration. This architecture consider both proper work frequency and hardware cost, with high hardware implementation efficiency. To meet the high-bandwidth memory requirement of the inter-prediction module, we design a reasonable reference frame data buffer architecture.An integrated design of AVS motion compensation decoder system is proposed based on fully academic and experimental analysis in this paper. Motion vector generation unit, prediction unit and reconstrution unit are all explored and implemented on hardware view. Some IPs are obtained, some of which are simulated and validated. The one-up design and research have significant academic and practice essentiality.