Design And Verification Of AES Encryption IP Core

The Advanced Encryption Standard (AES) issued by the National Institute of Standards and Technology (NIST) of the USA in 2001, is supposed to replace DES, and has become the new widely-used symmetric block cipher standard. A lot of efforts have been made on the various hardware implementations of the AES algorithm. Some of them focus on achieving extremely high throughput by using pipeline architecture, while others focus on designing low-cost and low-power devices. Given the specific requirement of portable devices and mobile terminals, the thesis presents a strictly compliant AES IP with an acceptable trade-off between area and performance. In order to reduce the area, an equivalent encryption structure is proposed, and a 32-bit data path is developed by sharing operation blocks between encryption and decryption as well as between round function and key expansion. By introducing composite fields Sboxes can be efficiently implemented with combinational logic. Two approaches of factoring of MixColumn and its inverse are explored. Bit-level resource sharing is fully employed by using common subexpression elimination. The suggested reconfigurable architecture of key scheduler is capable of performing forward key expansion for encryption and reverse key expansion for decryption in an on-the-fly way for all the three different key lengths. The AES IP is developed with a universal interface and can be easily integrated into SoC chips. Thorough functional verification is applied as well as timing verification. The implementation consumes 22.6k gates in SMIC 0.18μm technology. The throughput at the maximum frequency of 100MHz is 188Mbps for AES-128.