Design Of Analog Baseband Circuit For GSM Zero-IF Receiver

In this paper, based on research and analysis in zero-IF receiver architecture principles and characteristics, the circuit adopts the avtive RC topology to achieve low-pass filtering, the third-order Butterworth channel selection filter prototype is realized through the leap-frog method. As DC bias source of system, a bandgap reference which is stability with temperature and supply voltage designed. The capacitance matrix is used to tune the cutoff frequency with the consideration of the varieties of the temperature and technology. With merged function of the adjustable variable-gain amplifers, the output signal can accommodate to the dynamic range of the following ADC. The active-RC baseband filter uses a servo loop for dc-offset cancellation, which can prevent the operational amplifier saturation. The power supply voltage of the chip is 3.3 volts, which is integrated in TSMC 0.18-μm CMOS mixed signal process. Measured the baseband circuit performance includes a -3dB bandwidth of 200 kHz, programmable gain over 41-dB range in 1-dB steps, the noise corner frequency of operational amplifier is 4.7 kHz. The total area is 0.372 mm2, power consumption is 4.95 mW.In addition to the discussion of the structure, the EDA tools of Cadence is used for circuit simulation, layout and verification.