Design Of Hardware And Implementation For Intra Prediction Decoder Based On H.264

The application of multimedia video compression technique grows very rapidly with the development of multimedia information technology and digital signal processing technology.Then the new video compression standard H.264 comes out. Compared with the MPEG-X and H.26X compressed video standards that were establish before, the H.264 standard can increase the compression ratio substantially at the same image quality case. So its foreground is very wide. A lot of company and research institute begin to study and make use of such new standard. Because the decoding complexity of H.264 is very high, only software implementation can't decode in real time. The design of decoder must be implemented with the hardware and software working together.The main thesis of the paper is the design of hardware and implement for intra prediction Decoder based on H.264. Paper consists mainly of two parts:The first part firsly analysed the intra-prediction mode selection algorithm of H.264, then a new Intra₁6×16 mode selection algorithm and Intra₄×4 mode selection algorithm were proposed in this paper after analyzing the process of intra- prediction. The algorithm reduces the intra-prediction complexity greatly while maintaining coding performance very well.The second part is design of hardware and implementation for Intra prediction decoder based on H.264. First of all, the division of decoder system architecture and the division of hardware and software are accomplished according to the characteristics of video compression standard.And the overall structural design of intra prediction was proposed , including the design of input and output interface and the design of internal structure; then the optimization design was highlighted proposed, including the optimization design of the intra-prediction model and the parallel reconfigurable design of intra-prediction, making the system speed and complexity and resource consumption to achieve a balance;on the basis, the intra-prediction models are established, used Verilog hardware description language to transplant their RTL code, and completed the modelsim simulation of module. After the simulation, synthesized in the FPGA with Xilinx'XST tools, the highest frequency can reach 192MHz at the last, to meet the request of real-time HDTV decoder.