Design Multifunctional General Reconfigurable DSP Processor Based On TTA Architecture

Application-specific instruction set processors is a suitable choice as processors are being selected for the needs of digital signal processing applications. The ASIP design based on Transport triggered architecture has some good features, simple, programmable, automation. Thus the TTA can overcome the limitation of current ASIP design and could get the processor which satisfies target application as fast as possible.TTA can be viewed as a number of Functional Units performing operations, which are connected by a transport network, The FU are implemented using hybrid pipeline to allow for maximum scheduling freedom. The valid bit of TN can control pipeline and lock signal, meanwhile this paper demonstrates how to tailor the number of FU, Bus and define the operand register, trigger register, result register and function of FU.After the definition of instruction, Fu and TN, the process of program is visible so that more instruction level and data transport level parallelism can be found.This design is optimized for DCT in Audio/Video domain and FFT in communication domain. The target is design a multifunctional processor optimized for this two algorithms. And it could be shown that the processor has good performance and low power & resource. Beside, MOVE Framework can design some special function unit that can speed up target algorithms. This design has designed some special function unit for DCT and FFT. Via simulation, the performance of speed increases 50% after adding the special functional units.We have researched a design methodology that implements multiple algorithms in one processor. So it can implement some complex algorithms like AVS on TTA through these design methodology.