The Study On Self-Recovering Fault-Tolerant Controller Design Based On Hardening Token

As the feature size of integrated circuits(ICs) decreases to nm,the working voltage is dropping constantly,the working frequency is increasing dramatically, and the integrated density is rising drastically.Consequently,the soft error rate (SER) become higher and higher.As one of the critical applications of the ICs, controllers play significant roles in micro processors,whose capacity of soft error tolerance directly determines the robustness of micro processors,even the whole system.On the other hand,the ever-increasing scale and complexity of IC design make the cost of automatic test equipments is more and more expensive,and testing controllers is hard especially.Therefore,the design of controllers with self-recovery mechanism and built-in self-test function is drawing more and more attention.There are two types of soft errors,SEU(Single Event Upset) and SET(Single Event Transient),and the research of SEU tolerant controllers design is developed in the thesis,the main work of which is showed as follows.Initially,Chaitin's algorithm is improved to split FSMs,and the algorithm is implemented by C++ program which can generate Verilog and other files of various self-recovery structures for synthesis and simulation.Then TMR-Token and DMR-Token,collectively referred to as Hardening Token structures,are presented combining the token logic with TMR(triple modular redundancy) and DMR(double modular redundancy) respectively.Both presented structures can tolerate SEUs in state registers by the self-recovery mechanism.If an SEU happens in one copy of token registers,the voter of TMR-Token will filter it because the other two copies keep right,while DMR-Token will prevent token outputs from turning error according to the inconsistency of two copies.Finally,Bypass Pipeline(BP),TMR-Token and DMR-Token are compared on some aspects such as soft error tolerant performance and the area overhead.The results appeal that the presented structures can tolerate soft errors in token registers, which cannot be achieved by BP.Moreover,their additional time delay is negligible and the area overhead is less than 5%and 3%respectively,compared with BP.