The Research On NoC Test Scheduling And Mapping Method Concerning Low-Power

With the rapid development of semiconductor technology more and more processor units are integrated in a single chip. The shortcomings of traditional shared bus is lack of flexibility, which can not satisfy future SoC design requirements. Some researchers advise that bringing internet technology to chip. Hundreds of resources are connected through network structure which makes communication and computation alone. This structure is called NoC (network on chip). NoC is based on packet switching and the use of global asynchronous local synchronous communication mechanism provides good parallel communication capabilities, which solves many problems of bus-based communication.The object of NoC is to integrate large circuit in a single chip. Area, power and delay are still constraints of NoC design. The scale of NoC circuit is very large based on nm technique, so power is the most important constraint. Research on power consumption is becoming hot spot in NoC domain. Many researchers are studying the smallest power consumption of NoC design. For the problem of test scheduling and mapping concerning low power the main work of the thesis is as follows:The reuse of on-chip network as a test access mechanism has been proposed to test NoC-Based system recently. However, the test scheduling problem becomes very complex with limited on-chip resources such as channel. Test scheduling algorithm is tradeoff among test power, test time and total test cost. An optimized test scheduling method was proposed, which consider both test time and test power factor. With the premise of reducing the overall test time of all the cores, the location of Input/Output pairs and the optimized sequence of IP cores scheduling during test are selected according to the minimum cost of all cores. Experimental results show that the test time and overall cost is decreased and the efficiency of the test is improved in NoC parallel test.A low power mapping method was proposed in this thesis for NoC mapping problem based on analyzing the relationship between communication power and communication flow. In order to low down the communication flow of NoC, the proposed method first uses approximated pre-mapping, which maps the larger communication flow IP core to the position close to other vertexes. In mapping step we use the result of pre-mapping step to search better solutions, which fulfills the mapping process from IP core in communication task graph to resource vertex in NoC architecture graph. Experimental results show that communication flow is decreased and it is suitable to solve mapping problem with low power.