The Research On Low-Power And Data Compression Techniques In SoC Test

With the swift development of the system integration and processing technology,especially the emergence of System-on-a-Chip(SoC),Integrated Circuit(IC) has entered a new period of development.SoC adopts the technique of reusable Intellectual Property(IP) core,and maps the whole system(or subsystem) to a single chip,so it not only greatly shortens the development cycle,but also can reduce the size of product,improve system overall performance.The high level of integration and complexity of SoC pose challenges for SoC test.Generally speaking, SoC consumes much more power in test than in normal motion,which affecs the reliability,performance and cost of IC as well as battery life.With the increase in the number of IP cores integrated,the test data volume and test time increase quickly,which results in a significant raise in test cost.Scan structure is used to improve the controllability and observability of internal nodes of the circuit.It has also successfully been used in the current popular approaches of Design for Testability(DFT).Hence the low-power techniques in scan test have drawn significant attentions of academies and industries.Today test data compression is a direct and effective way that can resolve the issue of SoC test data volume.It can decrease test data volume and test time of IC without losing fault coverage.The main work of the thesis is as follows:For low-power testing,a low-power scan chain architecture based on selective trigger is proposed.It is available by changing traditional scan design using a scan register,whose length is equal to that of scan chain.It can efficiently reduce dynamic power in shift cycle and increase the scan clock frequency.The test data that our architecture requires is difference test vector set,so we don't require a separate Cyclical Scan Register(CSR) in decompression after encoding lengths of runs of 0s in the test data.The experiment results on ISCAS'89 benchmark circuits show that the proposed technique is more superiority to reduce average power during scan test than traditional scan design.For test data compression,a new test data compression technique based on encoding run and alternation sequences is proposed.It is a variable-to-variable-length code based on encoding lengths of runs of 0s and 1s,as well as alternating bits in test sequences.The code word consists of prefix and tail, the scheme uses prefix to indicate the type of sequence.Due to its simple architecture,the additional hardware overhead that the decompression circuit requires is very small.The experimental results on ISCAS'89 benchmark circuits show that this technique can efficiently compress test data.