ASIC Design And Implementation Of EoPDH In Deep Submicron Technology

In this paper,it mainly introduces the application specific integrated circuit top-down design flow in the design of 16 El EoPDH used in PDH system.First,it presents some basic concepts of the ASIC briefly,and discusses the architecture design which benefits synthesis and testability. And then,a detailed description of how to set constraint scripts on EoPDH in the synthesis flow by using the Design Compiler tool is given.Besides,EoPDH ASIC verification is also studied particularly in the paper, including dynamic simulation,static timing analysis and formal verification. Dynamic simulation is divided into module verification and system verification in the hierarchical testbench platform. Furthermore,two principles,which includes step-by-step verification and static/dynamic co-verification are suggested in static verification of EoPDH.By using such verification methodologies,we can not only verify the function and performance of ASIC design fast and effectively, but also give some useful advice for the optimization of design,and ensure the success of EoPDH.Now,the controlling chip of EoPDH has been made in Fujitsu,whose character size is 0.18μm and which uses five metal routing layers.Testing results show that EoPDH works properly and the requirements of spec are well met.