Research On The Digital Front-end Of Demodulator Compatible With DVB-T And DTMB Protocols

With the development of digital television technology, the tendency for broadcasting television to move from analog to digtal becomes irresistable. A variety of transmission standards has been developed and applicated, especially Europe's digital terrestrial television transmission standard DVB-T has been used all over the world, and now China has also developed its own standard DTMB. At present, the receiver chip design which is regarded as one of the core technology of digital TV system, in particular, the receiver chip are compatible with two or more standard.As an important component of a digital television receiver system, the digital front-end module plays an important role, shifts digital IF signal to baseband so as to decrease the data rate. In this paper, on the basis of thorough study on the DVB-T and DTMB standards, the author proposes a novel digital front-end module in digital TV receiver design solution compatible with two standards.The main features and contributions of this paper are as follows:1) According to market requirements, proposes a digital TV receivers solution compatible with two standards, and research the algorithm and hardware architecture of digital front-end module.2) Use the direct digital frequency synthesizer based on LUT to generate orthogonal signal, and propose new architecture to reduce the area of ROM to 344 bits,and the SFDR is 63.58dB. At the same time of digital down converting, compensate the carrier offset only changing the control word of DDFS. Meanwhile applied for a patent, the patent number is 200810202482.3.3) Use the high-performance interpolator based on lagrange polynomial to achieve arbitrary transition of the sampling rate. Improve the Farrow architecture in order to speed up computational speed of interpolator. At the same time of the sampling rate transition, compensate the sampling offset just only changing the control word of interpolator.4) This digital front-end module has been implemented and verified in Xinlix Virtex-4 serial FPGA. Finally it is proved the design can meet system request.