Behavior Model Design For AVS Video Decoder

To promote the development of national audio and video industry, the AVS Working Group was founded by Ministry of Information Technology in June of 2002, the group is responsible for making China's own audio and video standards. In March of 2006, the second part of AVS serials standards-AVS P2 was published, it mainly aims at applications about HDTV and high density storage.Systemverilog is a language used for hardware design and modeling, it supports OOP .OVM is an open source methodology developed by Mentor and Cadence, the methodology based on Systemverilog realizes a TLM mechanism. We use OVM in this article to build a behavior transactional level model for an AVS hardware decoder; the model can be used as a reference for RTL level design in the future.This thesis mainly includes following contents:1. At first, we introduce the current development of video compression standards and the development of AVS video decoder, point out the importance of system level modeling in modern SOC design.2. Then we analysis the computing complexity of AVS video decoder software, make a plan for hardware-software partition and pipelining for the decoder SOC.3. Then we builds behavior models for hardware sub modules in the decoder SOC, including variable length decoder, inverse quantizer, inverse transformer, intra prediction module, reconstruction module, motion compensation module and loop filter module. To ensure the correctness of the models, the simulation results are compared with results from reference software.4. Finally, we made a simple conclusion of the experiences we got in this item and point out the future works.