Research Of OTP Memory Design

With the development of manufacturing technology,ultra-large scale integrated circuit design has entered the ultra-deep sub-micron era.SOC(System on chip) has emerged.In the near future,the various functions of memory chips will occupy most parts of the SOC.In order to meet the job requirements,memory requirements of SOC chip are getting higher and higher.On the market at this stage a variety of programming nonvolatile memory cells require additional manufacturing processes, special materials,and require different thickness of gate oxide,which have increased the memory design complexity and manufacturing costs.In this paper,two kinds of standards CMOS technology memory cell structure are introduced.Use of gate oxide breakdown as the object of study,we have proposed and improved Tri-transistor memory cell structure;Moreover,based on the traditional floating-gate EEPROM structure,we have proposed a new structure of the EEPROM memory cell with single-poly floating gate.The two storage structures do not require additional manufacturing processes and optimize the shortcomings of the traditional memory. Making these two kinds of storage structures in terms of cost and reliability have a great advantage.In this paper,we have studied the gate oxide breakdown model,with an in-depth analysis and discussion of the two types of breakdown with the trap is generated,and we present a gate-oxide antifuse programming structure.With the consideration of the drain bias on the impact of TDDB,we have optimized the anti-fuse structure,which improve the programming speed and data storage reliability.Based on the traditional floating-gate EEPROM structure,paper also present a possible single-poly floating gate structure of memory.We also analyzed two kinds of electron injection model and the different of two programming models.In the text,we used MEDICI to simulation the influence of drain bias on the gate oxide antifuse structure and the programming model of floating gate structure.Finally,we have discussed the design of the overall structure of OTP memory in the paper.For gate oxide breakdown OTP memory,we present a viable NOR array structure and current sense amplifiers.