Design And Implementation Of A Random Numer Generator

The random number generator is significant in the encryption security technology. In the paper, the international general encrypting safety typical and the project's requirements are combined to make a good random number generator by random factor in the product chip. The sample clock is created by the oscillator circuit in the chip. The initial source of random numbers is obtained by processing the instantaneous data stream and data flow for controlling. A mixed circuit which is made up of a linear feedback shift register and a cell automated shift register is designed. Then, the initial random seed is input into the circuit and improved. The seed with better randomness is output. The random number of mixed circuits processed by SHA₂56 is diffused to get good character number with good randomness. A tool for testing the random number is programmed by C language. The number created by the random number generator is tested by the tool. It is a good random number.The RTL-level code of the all modules is written by Verilog HDL. The completed random number generator is simulated by the VCS tool, and synthesized by the DC tool. The parameter of performance in the circuit is obtained. The delay of the critical path is 6.3 ns. The power dissipation is 2.88mW. The result proves that the Random Number Generator in the paper designed is correct. The design achieves the goal of speed, power and area.