Study Of Data Control Bus Based On Multicore Package Processors

In the recent years, higher bandwidth and more integrated service have become an inevitable trend of network development. In order to deal with such a tendency, multicore package processors were applied in the network environment. The multicore package processors can provide both high performance process ability and programmable character.In network based on the multicore package processors, data transmission efficiency was highly affected by the bus interface of the multicore package processors. Through the study of the data transmission structure and mechanism, a type of data control bus applied in multicore package processors was designed to control the data transmission between multicore package processors and devices in the link layer. The data control bus can retrieve the state status from MAC devices, inform the multicore package processors to read it, and assert flow control to MAC devices, under 32bit full-duplex or 64bit half-duplex working mode.The paper completed the RTL design, built the reference models of the data control bus and the BFM of MAC device IXF440. Through the testbenchs constructed by these two models, this paper finished function verification. Furthermore, the synthesis result reported by Design Compiler showed that the data control bus was able to be operated at the frequency of 104MHz. Last, this paper completed the formal verification and function verification to the netlist.