Design Of Frequency Synthesizer Based On PLL

With the integration density of integrated circuits continue increased, Phase-Locked Loop(PLL) as a way to implement the frequency synthesizer has become one of the key technologies in modern microprocessors. It plays a more important role in the microprocessor with the continuous improvement of clock frequency。This paper discusses the design of PLL Frequency Synthesizer System. First the composition and theory of PLL Frequency Synthesizer System are briefly described; the structure, working principle and the linear model of the modules are introduced. According to the design requirements the design solutions and principles were discussed. The circuit design of Phase Frequency Detector, Charge Pump, Loop Filter and Voltage Control Oscillator has been given. In this paper the choice of the PFD structure and its function to eliminate the dead zone of the charge pump has been discussed. The non-ideal factors in Charge pump and the structure choice and low-power design of CP has been described. The LPF's impacts on loop performances are introduced. And the adjustment principle of the differential Ring VCO and the noise reduction methods has been described. Besides, phase noise and jitter related to the phase-locked loop frequency synthesizer has been analyzed and the noise reduction methods have been given in this paper. Then the performances of designed circuits are analyzed by simulation.The presented circuits design is implemented with 0.18μm 3.3V CMOS process. Experimental results show that lock time of PLL is about 100us, the range of VCO is about from 50MHz ~ 250MHz, jitter is about 200ps, the average power consumption is about 4mW. Also the results proved that PFD achieved the function and it has eliminated dead zone; Charge pump implemented the low-power design and its current match well. The differential ring oscillator has a good adjusting manner and anti-noise performance. The loop system achieved a good locking performance.