A Fractional-N Synthesizer For Multimode Multi-Frequency Transceiver Application

Many wireless communication standards have been issued, according to the requirements of wide bandwidth, high-data rates in recent years. The users want to use portable termals to access into a set of wireless networks. Therefore, in order for the transceiver to provide muilt-standard operation, it would require the duplication of many block circuit. Frequency synthesizer as one of the challenging blocks to design in such integrated transceiver have been given much attention in recent years. Low phase-noise, stable and programmable local oscillator (LO) signals should be available by the frequency synthesizer, because sensitivity of the integrated system is determined by the LO signals. A singlechip frequency synthesizer is proposed for the UHF RFID,WCDMA,IEEE 802.11 a/b/g in this thesis.Firstly, the importance of phase-noise and spurs in the integrated system is discussed. Then, the phase noise and spurs requirements are concluded based on the analysis of the protocols for UHF RFID, WCDMA, IEEE 802.11a/b/g applications. The thesis focus on low phase-noise single-chip AS fractional-N frequency synthesizer, characteristic works in the dissertation are summarized as follow:1.) Based on the analysis of the system framework and UHF RFID, WCDMA, IEEE 802.11a/b/g standards, design specification of the fractional-N frequency synthesizer for multimode application are derived.2.) The commonly structures of frequency synthesizer are discussed, and a suitable configuration of the fractional-N frequency synthesizer is proposed. According to the design specification, a wideband LC VCO is used to generate 3-4GHz outputs. The higher frequency (5.85GHz) I and Q signals are achieved by one mixer, compared with a QVCO the power consumption and chip area are reduced.3.) Phase noise behavior models are applied to found the effects of every blocks in frequency synthesizer. Under the behavior model, system parameters, VCO gain, current of charge-pump, loop width, phase margin, divide ratio, are verified and optimized. Finally, some suggestions are proposed to optimize the phase-noise.4.) VCO is the most critical block of frequency synthesizer. LC filters, high Q differential inductor and LDO regulator are implemented to optimize the phase noise of LC VCO. The BFMOAT technology is carried out in the layout of the frequency synthesizer to isolate the analog and digital area, what can suppress the substrate noise fedthrough effect.5.) A single-chip delta-sigma fractional-N frequency synthesizer for multi-mode application is implemented in IBM 0.13um CMOS 8SF process. The measurement results partly verify the founction of the delta-sigma fractional-N frequency synthesizer.