Impact Of Electrochemical Copper Plating Process Optimization On Voids Defect

With the downscaling of the semiconductor devices, backend interconnection plays a more and more important role for the density, speed, power and reliability of the chip. The improvement of interconnect material and interconnect technology became a key point of the progress of semiconducting manufacture technology. After 0.13μm technology node, Cu line has replaced Al line and become the mainstream technology. We have to face some Cu line issues after we use Cu to replace AL, such as the reliability with Cu and low K dielectric, and post-CMP (Chemical Mechanical Polishing) Cu line voids defect.In this paper, by studying the mechanism of Cu metal line voids defect, and comparing with results of ECP (Electrochemical Plating) process experiments, we can get optimal ECP production process. The resistance and stress of Cu film will be studied by different rotation speeds, anneal process and queue time (ECP to CMP). Finally we found the optimal ECP process conditions, which can improve the defects by several process conditions. Considering the cost and benefit of mass production, we selected the low rotation speed ECP process, ECP to CMP queue time control and suitable anneal temperature as the final condition. It can significantly reduce the defects and improve yield and reliability of products.