The Design And Verification Of E_agch Decoder

HSDPA system is now playing the main role in the program of air interface in the world. With the growing of the umber of UMTS customers, HSDPA will absolutely prosper in the future.E_AGCH is one of the new Transmission channel designed by HSDPA system, providing a UE (user equipment) the standard of absolute power. It is necessary in the HSDPA system. Of all modules in E_AGCH, VITERBI decoder is the most important part.But.It's difficult to deduce the needed memory space and enhance the decoding speed. So how to design a kind of VITERBI decoder with great performance is the key point to build the E_AGCH system.This thesis mainly focuses on the implementation of E_AGCH decoder algorithm. The main technologies together with the performance character of VITERBI decoder VLSI implementation are the key points to improve the performance of E_AGCH.In the course of building module, we use two methods to meet the need of simplifying.One is Simplifying the ACG part to deduce the number of state.The other is, in the track back processing, we devide the track into parts and this can deduce the memory space.The algorithm improved can help the E_AGCH satisty need of HSDPA system well.The function simulation is realid with the SPECMAN testbench. To cover all the situation of Verilog module, we design all kinds of case.The result shows the function of module is correct, function coverage is 100%, statement coverage is 98.86%, condition coverage is92.47%, toggle coverage is 94.26%. The module can meet the need of E_AGCH.