The Design And Study Of Analog To Digital Converter For Wireless Implantable Neural Recording System

With the development of microelectronic technology, the idea to implant electronic circuitry into the living body has come true. Implantable microelectronic systems with the features of low power, high integration and high performance, become a hot topic of biomedical engineering at present. In this paper, a successive approximation A/D converter(SAR ADC) with 12 bit resolution is designed for wireless implantable neural recording system. The circuit participated in the MPW and then was tested. Based on the test results of the first design, three aspects: system architecture, block circuit and layout, are investigated to achieve and optimize the performance of the proposed ADC.At the system level, a fully differential structure is chosen to extend the input dynamic range, improve the anti-noise characteristics and reduce the influence of non-ideal effect. Two capacitor arrays, which act as the high-8-bit D/A converter(DAC) to perform the successive approximation, can be used to realize the sampling and holding function. A resistor array acts as the low-4-bit DAC to improve the resolution. The A/D converter goes into standby periodically so that the power consumption can be reduced.Analysis focuses on accuracy and speed when the DAC is designed. The unit capacitor and the switch array are optimized so that the DAC can achieve a better tradeoff between accuracy and speed. When the comparator is designed, much attention is paid to relieve the offset voltage and save the power dissipation. Output storage method is adopted to cancel the offset voltage. To shut down the power periodically can reduce the power consumption of comparator. A bandgap reference based on current mode structure is designed in this paper, and a trimming circuit is introduced to obtain precision reference voltages.The circuit was fabricated on Chartered 0.35μm CMOS process with a 3.3V supply. The test results of the first design shows that the differential nonlinearity is high to 2.2LSB and the effective number of bits is 9.4bits. The simulation results of the second design shows that: Both the differential nonlinearity and integral nonlinearity are less than 1LSB. The effective number of bits is 11.9 bits. The core circuit of the second design consumes only 43.07μW and has a chip area of 543μm×509μm. Due to the layout improvement, the second design is hoped to get better test performances compared to the first one. The circuit has features of medium resolution, low power dissipation and small chip area, which is hoped to meet the requirements of wireless implantable neural recording system.