Studies On SOC Test Methodologies Based On Bus Scheduling And Buffer Addition

In system on chip (SOC) test research area, parallel test is one of the most effective test methodologies. Therefore, parallel test scheduling algorithm becomes a research hotspot. The main objective of scheduling algorithm is to improve the test bus utilization ratio and the parallelism of test data transportation. Currently, there are two main kinds of methods about the algorithms. One kind is about buffers addition between cores and test bus. The buffers are used to store test data. When test data need to be applied to the core under test, it can be read from the buffers. The other kind is about fixed test access mechanism (TAM) width assignment for each core, which achieves parallel test by transporting data to different cores at the same time. When data volume is larger, the first kind of methods requires bigger buffer size. Hence, its hardware overhead becomes higher. The second kind belongs to bus scheduling algorithm, which can not release test bus in time, when larger test data is transported to one core. The test application time becomes longer. To avoid the disadvantage of these two kinds of methods, this thesis improves the algorithms in two aspects.Firstly, this thesis proposes a scheme for test application time and buffer size co-optimization. On one hand, in the bus scheduling process, this scheme can adjust the number of input ports of cores by adding buffers, change connection bandwidth between cores and bus, improve the flexibility of the scheduling, and enlarge the scheduling algorithm's search space. On the other hand, in order to avoid the parallel test turning into serial test, we use the bus scheduling method to achieve parallel testing based on the approach with buffer addition.Secondly, we design a novel test scheduling algorithm for the proposed test scheme. In order to improve its flexibility, the proposed algorithm partitions the test set into some small subsets. Then, the test sequences generation should be done. At last, we get the test sequences that have larger Hamming distance with their previous test sequence. We schedule the test sequences according to the principal of time priority. That is, when hardware overhead and test application time conflict, test application time optimization should be considered firstly. Compared with previous test schemes, for ITC'02 benchmark circuits, experimental results show that the test application time and hardware overhead are reduced drastically. For example, for the benchmark circuit p22810, the test application time and hardware overhead are reduced to 67.6%, and 44.4% respectively.