The Optimization And Physical Design Of A 600MHz YHFT-DX Instruction Fetch And Dispatch Unit

YHFT-DX is a high.performance processor which based on the very long instruction word architecture. To deal with the storage problem of VLIW architechture, we introduced the compact instructions and the nonalign dispatching technique; and to improving the entire performance of the instruction fetching and dispatching, we used a brandnew prefetching technique.The control logic of the pipeline becomes more complicated by using these technique,and enlarge the spending of the hardware.It's a challenge to achieve the design goal of 600MHz for the fetch and dispatch unit.According to the design request of the YHFT-DX chip, In the paper we analyzed the existent problem and then optimized, and made certain the implement strategy for each module of the fetch and dispatch unit. By using the mixed design flow of the custom and the AISC, we finished the physics design and verification of the unit. The result of the PrimeTime showed that the delay of the longest path was 1.58ns , this achieved the design goal of the 600MHz. The main contributions are as follows.Firstly, Optimized the control mechanism of the fetch pipeline. Partitioned the pipeline over again, deleted the redundancy logic in the code.After that the area reduced about 13%, the dynamic power reduced 70% and the leakage power reduced 70%.Secondly, Improved the flow of the circuit design by summarizing the experience of the first edition. Considered the repetition of a module as possible as we can during the process of the circuit and layout design. a hierachical method and technique of prejudge the channel routing were introduced in the layout optimization, which increased the efficiency of layout design. Compared with the first edition, the area reduced about 18%, and the design period saved 75%.Thirdly, Seraching a method for the grid's programming of the power and ground before the layout design. The method which we used in the design was proved to be doable.Fourthly, Built the Liberty timing library and the LEF view for the DDP custom.bulit module, which must be used in the logic synthesis and physics design step.Fifthly, Completed the logic synthesis and physics design of the fetch and dispatch unit. Sloved all kinds of problems in the process of logic synthesis and physical design, and finally achieved the design goal of 600MHz.Sixthly, Replaced the standard cell in the synthetical netlist by the custom.built cell which has the same function with the standard cell. The method is not only improved the efficiency, and also satisfied the request of high.performance.Finally, Finished the function verification by using the simulation verification and formalization verification. Improved the efficiency by adding the compare assertion in the code.