Optimized Design And Physical Implementation Of The High Performance Trap Logic Unit

With the development of the microprocessor into the era of multi-core multi-threaded, the requirements on interrupt system have been improving. There are 88 types of interrupts or traps in multi-core multi-threaded microprocessor X. How to ensure the interrupt system can quickly collect and process all types of interruptions has become an important research topic.This paper studies the trap logic unit of X microprocessor, using the combination of semi-custom's and full-custom's design approach to realize the high performance trap logic unit. First, in the level of code, we reduced the number of logic units through resource sharing, removed a number of redundant bits of comparative statement by s suitable description which can reduce the cost of comparison logic, and improved the delay by resource replication. Second, according to the feature of trap logic unit, we design the high driving capability, special logic and high-speed standard cells, which enhance the ability of standard cell library to support the trap logic unit, and it optimizes the critical path delay greatly. At last, We customed 36 types of standard cells, and realized the layout of trap logic unit with reasonable strategy in 65nm process.In the case of worst condition of 65nm CMOS process and the medium wire load model, the synthesis frequency is 1.0GHz. After the trap logic unit is optimized, the synthesis frequency is 1.5GHz, and we finish the goal of optimizing our designs.