Study And Implement Of A Pipelined Loop Array Architecture

In recent years,more and more coarse-grained reconfigurable architectures have been proposed. Coarse-grained reconfigurable architectures become important due to its combination of the advantages of both ASICs and general processors. This paper describes a reconfigurable array architecture based on pipelined loop computing. That is, the array processor communicates with the main processor through the AHB interface.In this paper , we introduce the design idea of the PLAA ,and propose its design model. This architecture is based on pipelined loop execution model and directly facing to the character of programs. In addition , PLAA is designed as a hardware acceleration unit based on AHB, which improve its portability.To demonstrate the effectiveness and excellence of PLAA architecture,we build and model the PLAA on the SoC designer platform in SystemC language. After analyzing and optimizing the staple algorithms , we map the algorithms and the result shows PLAA has a higher performance than other similar systems.