The Design And Simulation Of Topology On Network On Chips

With the development of semiconductor technology, SoC (System-on-Chip) will become more and more complex in the future. SoC technology will integrate more processors and memory components in a chip. There are many limitations in traditional on-chip communication structure in the current design. Network on Chip ( NoC ) will be the the appropriate communication structure for MPSoC (Multi-Processor System-on-Chip).NoC topology has a great influence on the performance of the system. Network latency, routing algorithm, fault tolerance are related to the structure and topology. Common structures of the NoC are Mesh and Torus structures. In this paper, we proposed a network topology for NoC based on De Bruijn graph and designed two routing algorithms for the network. De Bruijn graph has smaller diameter, higher connectivity and more simple routing algorithm compared with other network structures.SystemC, which is maintained and developed by OSCI (Open SystemC Initiative), is a system-level description language for the system description. It is built on a series of C + + class structure and suitable for system-level simulation design. In this paper, we used SystemC to establish a system simulation model which can facilitate the NoC simulation, architecture research and network protocol development. This model can also accelerate the design and performance of NoC routing on RTL and be used for research of power consumption and latency.