Research And Implementation Of Block-pixel Based Fast Motion Estimation Algorithm

Motion estimation algorithm is one of the most important techniques in video compression standards. This algorithm transforms two neighboring frames into small amounts of motion vectors and differential signals which are stored and transmitted then, to reduce video temporal redundancy and achieves high compression ratio. There are several motion estimation algorithms. However, the method based on block matching is widely used because of its simple way to implement and good effect of estimation. In the process of application, the computation amount of this algorithm takes up nearly 40% to 60% of the total encoding computation, which is the major bottleneck for saving the video encoding time. Therefore, how to reduce the computation amount and improve the performance of block matching algorithm is one of the research focuses in image coding technology.In this paper, block pixel is introduced as a new processing unit to reduce the complexity of calculation and to improve block matching criterion and motion vector precision, which is one of the essential ways to develop new algorithm. In order to solve the problem of falling of motion vector precision after the use of block pixel, this paper introduces the fractional block pixel and the motion vector precision successive improved searching strategy. Local minimum is one of the inherent problems of block based matching. In order to reduce the chance of falling into this problem, the improved search templates and searching steps are introduced. Experiments results under subjective and objective evaluation criterion show that the proposed algorithm's searching speed increased by 23% and the PSNR increased by 1.5dB at maximum compared with the diamond search.With the development of video industry and widely-used video codec chips, a motion estimation hardware module is one of the main approaches to enhance the competitiveness of chips. In this paper, motion estimation search engine is designed in Verilog HDL. Every module in this searching engine is proposed and the structure and format of data storage is introduced. At last, each module is verified and results show that all modules work properly with accurate results, and achieve the expected demand.