Physical Design Of 600MHz YHFT-DX Microprocessor

As the CMOS technology continues scaling, the circuits' frequency and integration scale constantly grows, the parasitic parameters of interconnect have become a key factor in VLSI design. It increases the delay and power consumption and makes the crosstalk noises more seriously. The physical design of High-performance DSP optimization techniques will help speeding up timing convergence, decreasing power and area, increasing signal integrity and reliability. It has becomes one of the hot topics in physical design.The difficult of this design: First, how to achieve 600MHz in 130nm technology. Second, how to control IR-Drop with Ground Brounce of YHFT-DX is within 5% of power supply.For timing closure, the design methods in this paper, is the critical path full custom design, each CPU function unit is designed to custom and semi-custom IP, and centralized arrangement; In floorplan, 2 Level Cache control logic connect Core and an external device, is is arranged in the central chip, squared with its connected modules arounded; in the selection of placement optimization model, the first is two timing-driven placement optimization, the second is both timing and congestion placement optimization; In clock network planning, selecting a balanced tree clock distribution method, in the clock tree synthesis, restrict Buffer / Inverter size; The crosstalk is prevented before route, the crosstalk is fixed after route; In addition, setting the false path, Micro-adjust placement, useful skew, ECO and timing trade were used to optimize the timing. Practice shows that the design flow and physical design methods can optimize the timing can better meet the YHFT-DX chip timing requirements, reach 600MHz timing goal.For the IRDrop, set the part of the margin for IRDrop in the early planning stage of power network design; In floorplan, the large hard cores are arrangemented distributed; After power planning, adjust I/O cell arragment, and add vertical direction strips for standard cell area IRDrop. IRDrop analysis showed that these optimization methods can completely meet the chip IRDrop indicators, IRDrop and ground bounce and be strictly controlled less than 5% of supply voltage, the system reliability is increased.The clock tree covers the whole chip and it has large latency and load. It has a great influence on timing and power consumption of the chip. So decreasing the power consumption and clock skew becomes the main purpose of clock tree optimization. The YHFT-DSP uses the balanced tree topology to get good control of clock skew. And with combination of clock gating, a prominent reduction in power is achieved.The interconnect bus of YHFT-DX connect many modules with long length and have high transition rate. So the Signal integrity optimization becomes much meaningful to improve the timing, decrease power consumption and improve reliability of the whole chip. This paper analyzes the cross talk of YHFT-DX and studies the optimization techniques for Cross talk prevention and Cross talk fixed based on automatic P&R tools.At last, the Static timing analysis, are introduced in this paper.