Design And Implementation Of Decimation Filter For MEMS Geophones On FPGA

MEMS geophone has become an essential part of the new generation high-precision digital seismic data acquisition system,its excellent ability of detecting weak signals makes it capable to accomplish high-precision exploration mission.As the core component of MEMS geophone.the mission of decimation filter is to change high speed low bit-width data stream which is generated by front-end modulation circuit to low speed high bit-width data stream.Article major work is to design the decimation filter and implement it with FPGA.The background of MEMS geophone is introduced at first and the requirements of decimation filter is proposed.Then the structure of the decimation filter is determined,which is designed as three part:Front-end CIC filter to complete the high extraction and anti-aliasing; Compensation FIR filter to compensate passband attenuation and further extract; Terminal equiripple FIR filter as the system fine filter.Then the filter parameters which meet the design specifications is obtained through Matlab simulation.Finally,CIC filter hardware architecture is optimized,after that, the decimation filter is implemented on FPGA.Research results show that:1.Decimation filter designed can meet the multi-rate output requirements,dynamic range,signal to noise ratio, stop-band attenuation,pass-band ripple,and other properties are standard;2.Lower power consumption estimation are attained with Hardware architecture designed in this paper.