Frequency character measurer (also called sweeper), is a kind of instrument which tests frequency character of circuits. It is widely used in numbers of fields, such as radar and telecommunication, which provides convenient means for analyzing and improving circuit's performance. However, the conventional sweepers have some drawbacks—complexity, volume, multi-module and so on. Especially in high-frequency measure, large numbers of discrete components are easily affected by change of temperature and electromagnetic interference. Aiming at this, the theme provides integrated design and explores the hardware implementation method.The theme researches three key technologies deeply:Firstly, from the design of swept signal generator, the theme researchs DDS theory, and designs a compressed ROM method which improves compress ratio of the look-up ROM and spurs of DDS system. Furthermore, one DDS system with amplitude modulation and phase modulation is realized based on this theory.Secondly , in order to heighten working frequency, the theme researchs the pipeline technology, and improves it aiming at accumulator design, which makes the whole system work at lOOMHz system clock.Thirdly, from the method of frequency characteristic test, the theme researchs how to improve the speed of multibit mathematical operations and advances a high-speed serial division method with BCD code. And with the pipeline technology applied in it, the arithmetic is improved. Furthermore, it is applied in the design of the frequency character test module.On the foundation of the last three theories, based on the carrier of the large scale PLD EP1K100QC208 and MCU 89C52, this theme comesup with an integrated design scheme based on MCU and FPGA architecture. Verilog HDL is used as the design language. The theme completes the design of frequency character measurers. The measurer completes two main tasks: outputting swept signal and testing frequency characteristic. Those two key modules can be integrated in a PLD, which embodies the advantage of the PLD.The theme introduces the whole related conception at first, including frequency character test, DDS theory etc. Based on those, it advances the whole design scheme, including tools languages and carriers. And then the MCU circuits and peripheral circuit is introdued briefly. At last, the theme studies the theories of the two main modules and gives out the realization way.Aiming at FPGA applications, the improvement of ROM compression method and the high-speed division of BCD code are the two innovations of the theme. |