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The Parallel Topology Of The Circuit Analysis

Posted on:2009-12-31Degree:MasterType:Thesis
Country:ChinaCandidate:Y ZhangFull Text:PDF
GTID:2192360272459123Subject:Circuits and Systems
Abstract/Summary:PDF Full Text Request
In recent years, symbolic analysis of linearized analog circuit has been a major topic of research. The driving force behind this research is that symbolic analysis can obtain symbolic network functions with all circuit elements represented by symbols. It can improve the insight into the analog circuits, and therefore it can accelerate the design process of these circuits. But it is always limited to small-size circuits because of the exponential growth of the number of the terms(trees or loops) with the circuits size. So the symbolic analysis becomes the major topic of this article.In this paper, non-directed graph topological method and directed graph topological method has been applied to complete the symbolic analysis of the analog circuits. And the parallel topological analysis for circuits is proposed. The method combines node tearing with topological analysis to realize symbolically parallel analysis for larger scale circuits.The following works have been done in the implementation of the algorithm and its application.First, analyzed the advantage and disadvantage of the topological analysis method, and proposed a new method, the parallel topological analysis method.Secondly, proposed the parallel non-directed graph topological method which is applied to inactive network ; described the implementation of this method in detail; gave a example on applying the parallel non-directed graph topological method to an inactive network.Thirdly, proposed the parallel directed graph topological method which is applied to the active network; described the implementation of this method in detail; listed the rules of choosing the tearing node; gave a example on applying the parallel directed graph topological method to an active network.The parallel topological analysis method combines node tearing with topological analysis to realize symbolically parallel analysis for larger scale circuits. The method not only successfully enhances the applicability of symbolic analysis, but also improves operational speed and efficiency.
Keywords/Search Tags:Circuit Analysis, Symbolic Analysis, Node Tearing, Topological Graphs
PDF Full Text Request
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