A 14 Bit Sigma-delta Adc Using Feed-forward Structure

Starting with system modeling, this thesis completes a 14 bit Sigma-Delta ADC which can be integrated in SoC. The signal band is 3.9 KHz and the frequency of sampling clock is 2MHz.Based on low cost implementation, this thesis chooses 2nd order modulator structure in analog domain. First, the thesis analyzes several typical 2nd order system structures, and chooses a feed-forward one as the modulator structure which can work reliably under low power supply. The thesis also analyzes various types of circuit noise which can deteriorate modulator performance. Through MATLAB modeling and simulation, the thesis evaluates the influence of these noises on SNR, and makes circuit specifications for modulator.Then, the thesis analyzes digital decimation filter based on CIC structure and Rotated Sinc structure with the viewpoint of performance and cost. Rotated Sinc can reach better aliasing suppression performance, while CIC can be realized in smaller area. With a trade-off between performance and cost, the thesis chooses two stage CIC structure to realize decimation filter.Finally, the thesis discusses circuit realization of modulator. Two-stage operational amplifier structure is used. The first stage is a folded cascade amplifier and the second stage is a common source amplifier. With the consideration of application field and hardware cost, the thesis chooses a simplified bootstrap switch as sample switch. Also, the thesis discusses realization of comparator, clock generation circuit, current source, bias and DC reference generation circuit.The proposed converter is fabricated in TSMC 0.18um 1P6M process. The die area is only 0.3mm*0.4mm (analog domain modulator is 0.3mm*0.2mm). The simulation result shows that the total power consumption is only 2.1mW. At 2MHz sample frequency, the converter achieves 83.9dB SNR and 91dB SFDR for a 1.2 KHz input.