Ip Design For Ahb Bus Control

IC design technology into the UDSM, the chip design capability and technological capacity has been greatly improved. Early digital IC design based on timing-driven, now the main SOC design based on IP reuse design. SOC chip's overall performance, power systems and modular design is the complexity of the design by the internal bus to decide. Bus system design is to determine SOC design the key to the success or failure.ARM launched by the AMBA on-chip bus is the industry's most popular bus standard one, a large number of IP SoC design engineers and system integration engineers wider use of AMBA bus in the design.AMBA AHB bus, including standardized system bus, ASB bus and APB external bus. AHB bus mainly used for CPU, DSP and the DMA and other high-performance interconnection between the modules, from the main facilities, equipment and infrastructure from the three components. In this paper, research study in the internal SOC chip interconnect bus standard and IP design process on the basis of full understanding of AHB bus protocol, the completion of the monitoring system used in the SOC chip EEYE AHB bus controller design. SOC chip EEYE AHB bus controller used to achieve the shared storage unit, saving the cost of the system memory. EEYE with AHB bus in the concrete application of chips, made by bus controller management system to reduce the gated clock chip power consumption of new ideas, and realize the circuit with this feature. AHB bus controller to take top-down design, divided into arbitration, decoder, mux, register, gated clock signal modules. The entire circuit with hardware description language VERILOG completed logic design, through the MODELSIM logic verification, and completed a comprehensive DC. According to the company and the industry IP design specifications and processes to achieve the AHB bus controller of the IP.