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Network On Chip (noc) Switch Fabric Design And Research

Posted on:2012-12-05Degree:MasterType:Thesis
Country:ChinaCandidate:Z Z FuFull Text:PDF
GTID:2208330332486800Subject:Communication and Information System
Abstract/Summary:PDF Full Text Request
The requirement of system-on-chip in the aspects of area, complexity and function become serious. The number of processing units and the interconnection throughput in system-on-chip are needed to be improved. The global interconnect delay in system-on-chip is the main problem, which will affect the performance of the whole system. The architecture of Network-on-chip, which is based on packet transmission, is one effective solution to resolve the interconnection of multiple IP cores. NoC is the widely concerned topic recently.In the solution of network-on-chip interconnection, the router is the key component of network-on-chip that contains the buffer, switch, arbiter, and control logical module, which implement the routing of data flow and the store-forward of packet. The infrastructure of the router affects the data transmission in network-on-chip significantly. This paper studies the router architecture and the implementations of some key modules, virtual channel, switch, and etc.In order to reduce the network congestion and improve the throughput, a plenty of buffer resources are required. The buffer which is in the input port or the output port of each processing element could implement the retiming function. So in the design of router, the suitable buffer regulation, the number of buffer and the depth of each buffer will effect the packet transmission of network-on-chip.The arbiter of network-on-chip could adopt different arbitration mechanisms, such as fixed priority arbitration, variable priority arbitration, round robin mechanism and matrix arbitration. This paper analyzes those different arbitration mechanisms and implements the round robin and matrix arbiter, finally compares the behavior of them. In the structure design of network-on-chip router, the crossbar switch is an important module. The area, bandwidth and power consumption of crossbar switch will affect the performance of network-on-chip router curiously. The crossbar switch needs high speed and provides effectual solution to resolve the competition. The design and implementation of switch may adopt different schemes, such as the data choice pathways which is based on tri-state gate or multiplexer. This paper implements the crossbar switch design by the iSLIP algorithm.
Keywords/Search Tags:network-on-chip, router, arbiter, crossbar switch, virtual channel
PDF Full Text Request
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