Fdp-sopc Chip ASIC Design And Implementation Of Part

With advances insemiconductormanufacturing processes, dramatically increasing development cost, shorter time to market and flexibility demand, ASIC designs are more and more difficult.Meanwhile, reconfigurable devices are developing fast because of its flexibility and less development cost.But intrinsic shortcomings of reconfigurable devices, for example, high power, low speed, etc. induce difficulties in complex designs realizations.So people began to consider combination of ASIC and reconfigurable device on a single chip, which is SOPC.First, this paper analyzes the characteristics of the existing SOPC,implements the hardware platform for evolve, and proposes the SOPC design and verification process, including system design, FPGA IP core supporting software, FPGA IP hardware core, hardware and software co-verification and so on.Second, according to the system design requirements, FDP-SOPC is a hardware platform chips using 0.13um process.A dedicated interface is designed for the high-speed and reliable data transmission between CPU and FPGA IP, and CPU can set FPGA IP by this interface.The accelerator in this interface can improve the implementation time of evolve algorithm.Third, ASIC part of the verification meet test convergence by the IP block verification of random test vectors and converage check,System verification and FPGA prototyping verification of co-verification. In order to reduce the difficulty and workload of the back-end implementation, FPGA IP Hardware core is proposed.Fourth, the SOPC chip is taped out by 0.13um CMOS process, die size 4.5mm X 6.2mm. Chip final test results indicate that the chip can work properly, and meet to evolve applications.