Nano Technology Parasitic Extraction Optimization

With the development of semiconductor IC stepping into nanometer, the demand of DFM (Design For Manufacture) increase exponentially. The various Process Variation in Manufacturing challenge the product yield greatly. In Nanometer technology, the high density and complication of interconnect wiring directly affect and control IC circuit's performance or yield, so it becomes more and more critical and important to extract the effective interconnect parasitic RC for circuit simulation. Now, the current parasitic RC extraction file/flow doesn't consider much about process variation effect in manufacturing, thus there's mismatch between the post-verification parasitic RC extraction/simulation and real silicon database, which means the parasitic RC extraction and circuit simulation (timing analysis) can't forecast or reflect the real silicon IC circuit performance. Sometime such mismatch will directly result in product (IC) failure and low yield.Base on such situation, we make a series of improvement on parasitic RC extraction files to upgrade its extraction accuracy and reliability in this thesis. More details as following:(1) Simulate following Process Variation Effect in parasitic extraction files.●Actual Wire shape (Etch)●Wire Edge Enlargement (OPC)●Wire Resistivity variation due to Width (CMP)●Wire Resistivity/Thickness variation due to Density (CMP)●Microloading effect (Thickness change at wire bottom & ILD variation)●Metal Fill(2) Create test structure, do post-extraction/simulation/tape-out/comparing.Thesis discusses what kind of process variation effect on parasitic RC, how to define/simulate those process variation in parasitic extraction file and optimize the parasitic extraction flow, then test & compare the difference between pre-optimized and post-optimized. The result shows that the difference between RC extraction/simulation and silicon data is improved obviously.