Applicable To Research And Design Of Analog-to-digital Converter Of The Wireless Transmission System

The direct conversion radio frequency (RF) receiver shows the greatest potential to meet commercial trends especially for Wireless LAN application. Except for RF frond-end, analog baseband interface is important to filter and digitize signal coming from down-converter. To be adaptive to large dynamic range requirement, conventional baseband circuit is realized by a combination of channel selection filter, automatic-gain-control (AGC) and Nyquist rate ADC. However there are several disadvantages of the AGC loop:1) subjected to presence of large interferences, allowable AGC gain is limited and AGC is generally distributed through the overall baseband chain to amplify signal and attenuate interference.2) AGC gain settings are fixed after setting behavior even though input signal strength might vary, this requires large headroom of dynamic range (DR) especially for high Peak-to-Average Power Ratio (PAPR).3) Large DR implies a longer setting time of AGC loop which is not allowable.An alternate, a less expensive way to improve DR of baseband without AGC is companding system, in which gain control works all the time adaptively during data processing. The input gain element compresses the high dynamic range input signal, which is then processed by the low dynamic range signal processor (filter and ADC) followed by expansion cell as output gain element. The compressing filter has been realized [1]. This thesis focuses on expanding ADC design for companding analog baseband interface. The pipelined ADC, based on switched capacitor (SC) technique, has most successfully covered resolution and sampling rate requirements of the 802.11 standard. In this thesis, a 10-bit 25MS/s pipline ADC with digital expander as back-end processor is designed in IBM 130nm CMOS technology at 1.2V power supply. The specification of ADC is derived from WLAN 802.11 standard. Then overall optimization of pipeline ADC in the format of stage scaling down is analyzed while special attention is paid to various error sources degrading ADC linearity. At the circuit level, high performance topologies of essential blocks have been developed such as two stage switched OTA with gain boosting and bootstrapping switch for highly linear sampling. Finally the pipelined ADC core consumes 24mW with 60.3dB SNDR,78dB SFDR and 76dB IMD3 is obtained. Combined with expander, extra 12dB DR is achieved with equal dynamic performance because companding takes place. Compared to conventional baseband interface, power dissipation is reduced by a factor of 3.3.The second part of this thesis is composed of the design and implementation of a sub-sampling flash ADC for IR-UWB receiver. The clock rate is 1.056GHz with a resolution of 4 bits. The front-end amplifier is avoided saving the power consumption due to using the averaging and Interpolation technique. The front end THA involves self-biasing to avoid deteriorating swing and linearity resulting from low power supply. An offset self-calibrated comparator is proposed to limit the input referred error low enough. Finally the post-simulation shows that the SNDR is 25.6 dB and SFDR is 35.9 dB and the chip's measurement result shows 19dB SNDR and 31dB SFDR.