Ldpc Decoder Implementation Of Research

Low-density Parity-Check(LDPC) code is distinguished in channel encoding and decoding realm for its low implementation complexity and near-to-Shannon-limit performance. Until now, LDPC codes have been widely used in various wireless communication standards, such as IEEE 802.1 In, IEEE 802.16e, DVB-S2, CMMB.However, the implementation of LDPC decoders still has some difficulties:On one hand, the long code-length and substantial parallel-operation inevitably bring large-area logical units and storage array; In order to support multi-operation and improve adaptability, almost all LDPC codes in communication standards support multi-mode, which makes request about the configurability of LDPC decoders; The address-conflict problem occurring in some parity-check matrixes of LDPC codes affects the timely use of information in the decoding process, and decreases the decoding performance. In regard to these difficulties, this dissertation proposes the ASIC implementation of LDPC decoder from the aspects of low-cost, multi-mode and address-conflict. The proposed LDPC decoder implements the support of multi-mode through extracting the character of parity-check matrix and abstracting decoding process. By re-using the computation unit and optimizing storage unit, the proposed decoder has a low complexity.On the other hand, the increasingly fast updating speed and complex mode of communication standards bring up higher demand for the flexibility, extendibility and design period of LDPC decoder. Although ASIC design has the advantages of high-performance and low-area, its shortages of high development cost, long development period and low-flexibility are inevitable. In respect to these problems, this dissertation proposes a fully programmable LDPC deocder on multi-core processor platform. By analyzing the communication traffic, parallelism, amount of computation of decoding algorithm, this dissertation proposes optimized division and mapping method of the decoding algorithm, and presents the implementation result of an (576,288) LDPC code. The implementation result shows that the proposed division and mapping method enable full use of each processor and high throughput.