Hdmi Buffer Design

Semiconductor technology develops so fast that it can reach 40nm for feature size in IC process, which was still 0.25um several years ago. With the development, feature size will be more smaller and more devices can be made in the wafer, but at the same time many problems occur such as design complexity, reliability and cost.A buffer based on OTA mainly is introduced in CMOS 65nm process in this thesis. The buffer is desiged for CEC in HDMI technology. A complete flow and technology innovation are introduced here, including circuit frame, front design and simulation verification, then the layout implement, at last the wafer taped out and lab evaluation;Then it also introduced how to update the design in newer process, make the area smaller and cost less, which gave an evidence of Moore'law on semiconductor technology development.Some points are also provided in the thesis, including design experience and solution in deep-sub micron techology. Specially, some key points in deep-sub micron layout such as WPE and STI are introduced.