| Electronic packaging is an essential step to transform integrated circuit chips into practical electronic products. It provides electronic interconnection, mechanical support and protection to the IC chips, and significantly improves the reliability of the chips. Flip-chip packaging starts to become a mainstream of high-density electronic packaging method to cover the requirements for high-performance electronic packaging system. Furthermore, three-dimensional packaging offers a new direction for higher density electronic packaging. In a certain electronic packaging system, the coefficients of thermal expansion (CTE) of silicon chip, substrate, solder balls, underfill and other materials are quite different. Thermal induced stress is prone to exist in the packaging process and produce adverse impacts on the performance and reliability of the chips. It has great significance to improve the reliability of electronic products through an effective method of measuring the stress generated in the process of electronic packaging, which can help to understand the impact of packaging process conditions and parameters on the stress in chips.Piezoresistors are manufactured on SOI (Silicon-On-Insulator) chips to form a stress sensor chip, relying on semiconductor piezoresistive effect. The stress distribution on a silicon chip can be obtained by stress sensor array on the sensor chips. Platinum resistors are designed to be temperature sensors for measuring temperature variation during packaging process. Piezoresistive coefficients of the piezoresistors are calibrated using four-point bending method of calibration, and the temperature coefficients of piezoresistors are calibrated by boning senor chips to flexible substrates. These coefficients are used for calibrating the stress during the packaging process with great temperature range.Piezoresistive stress sensor array chips (5×5array,8mm×8mm) are flip chip bonded to PCB (Printed Circuit Board) substrate, and the stress generated by the flip-chip process is approximately200-300MPa. The stress at the edge and corner of chips is slightly larger than the central portion. Study demonstrates that the bonding stress induced by large-size chips is greater due to a larger degree of deformation in the flip-chip process. The flip-chip bonded chips are then filled with different kinds of underfills, the stress generated by curing process ranges from30to120MPa. The stress increases with the increase of underfill CTE and the curing time. Underfill stays in rubbery state in the curing process when its glass transition temperature (Tg) is lower than the curing temperature, leading to a greater deformation, thereby causing a greater curing stress. During the underfill curing process, the chip stress increases first and then decreases, the chip stress pick up at the end of curing when chip begins to cool down. It was found that chip stress decreases with the increasing number of cycles, but the stress in chips with cured underfill does not change significantly.Three-dimension stacked packaging is formed by SMT adhesive. The stress induced by stacked chip packaging is approximately60MPa when the stacked chip is the same size of the bottom chip. For small-sized chips, and laterally offset laminate Assemblies, the stress generated on bare chip surface is smaller than the surface area covered by the SMT adhesive, and the stress induced by multichip stacked packaging can be neglected. Silicon substrate (10mm×10mm) is also used for flip-chip bonding, stacked chips are bonded to the bottom of silicon substrate by SMT adhesive, and the stress on the top layer chip is smaller than that of the bottom chip. |
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