Based On The Risc Core System Software And Applications

With the development of chip design technology, the complexity and superiority of Soc (System On a Chip) is increasing constantly. This brings new and greater challenges to system software and hardware designers. When system software is in design, the architecture of the hardware should be considered. The hardware software co-design is more needed to SOC than any other systems. The only way to fit the design efficiency is to adopt embedded processors running with customized software. This is a new problem to system software design.At the same time, software simulator is widely used in many research domains. It is useful to those who don抰 have actual target machines. On the other hand, these target machines will not persist for many years because of the rapid progress leading to new computers. In addition, simulators can provide a better environment for low-level programming than an actual machine because they can detect more errors and provide more feathers than an actual machine. Simulators are also a useful tool for studying computers and the programs that run on them. Because they are implemented in software, not silicon, they can be easily modified to add new instructions, build new systems such as multiprocessors, or simply to collect data.Considering all these reasons, the author surveyed traditional system software design tragedies and designed a series of development tools for the embedded RISC core with our own IP (intellectual property). These include an assembler, a linker, and a simulator.The content of this paper is organized as following:The first chapter is concerned with the traditional system software design tragedies.After that, we illustrate the RISC core architecture for which we designed these tools.We also mentioned the HDTV-integrated-source-decoder chip, an application of thisRISC core.We purposed and implemented an algorithm using single pass scan for assembler in the second chapter. Based on the output object file format, we also designed a linker.In the third chapter, we implemented an instruction set simulator (ISS) for the simulator target RISC core. We also illuminated each modules of this simulator.In the fourth chapter, to illustrate the using methods of these designed tools, we implemented an algorithm for audio signal A-rate Compress Extension as an example. Comparing and co-verifying the results between the simulation and the hardware of this algorithm running, we explained the process of software hardware co-design using this simulator.