Based On The Tm5 Mpeg (rate Control) Algorithm Based On The Pci Bus By Sweeping Video Acquisition System Hardware Design,

With the development of science and technology, digitalization of communication has been increasingly influencing the living style of people, and its excellent properties show best future. However, it brings up the big problem of too much data while it accommodates the need of the people. This drives it unavoidable to develop some algorithm to compress the digitized data. As far as multimedia information is concerned, especially the part of video information, the situation is more serious. It is impossible to realize multimedia communication without the compression of dada. For this reason, ISO has developed several international standards of data compression to standardize the compression algorithm and the organization of video data and audio data, therefore make the products produced by different companies compatible. Out of all of these standards, MPEG-2 has the widest implementation in the future. TM5 is a test model which is a world-wide implemented successful algorithm application for MPEG-2 standard. It exerts an important influence on the modification and generalization of MPEG-1/MPEG-2. Because the main focus of TM5 is algorithm research, not business application, it has opened free source code and exists some limitation in the practice. It is well known that scene changes often happen in our contacted video information. In the first part of this paper, we will discuss how to improve the rate control algorithm of TM5,in order to resolve the scene change problems.The second part of this paper will introduce the hardware design for the Enhanced Progressive-Scan Video Capture System based on the PCI Bus. The main outline included the specification of Enhancement Processor 1C and PCI Bus, how to generate the system control signals and achieve transmission complied with PCI Bus specification by use of FPGA design.