Risc Processor Instruction Cache Design And Its Optimization

The rapid development of information process technology and complex intelligent control method has posed a challenge to computer architecture designers . In order to met the requirements, the circuits with microprocessor as core are used wider and wider. Research and design in microprocessor architecture can promote the development of our national IC industry and satisfy market demand.The work in this thesis was part of a National 05' project which task was designing the "LongTengRl" microprocessor.There are four parts in "LongTengRl" microprocessor: Integer Execution Unit(IEU), Floating Point Unit(FPU), Memory Subsystem Unit(MSU) and Bus Interface Unit(BIU). The instructions are executed in pipeline. This paper discusses MSU's design, implementation and verification, implements the integration of the "LongTengRl" system and studies the optimization of instruction cache. As a crucial enhancing technology of instruction cache, the trace cache was also studied in this thesis.The research work of this thesis mainly includes:1. Analyzer of "LongTengRl" Architecture:2. Design and Implementation of Memory Subsystem Unit;3. Function simulation in three ways:4. Coding optimization for improving the speed of MSU.5. Timing simulation for verifing the setup/hold time:6. Study of the TraceCache Technology;"LongTengRl" is a complex microporcessor system. This thesis has contributed a lot to the designing of embedded microprocessor with full copyrights. Moreover, it provides an optional microprocessor core for urgent need in aviation field.