Balancing Technology Of Hf Digital Communications

In shortwave communication system, Intersymbol Interference is serious and signal is distorted extremely because of fading channel resulted in by the effect of multipath.The adaptive equalizer should be used in order to compensate channel characteristic and recover received signal correctly.Blind equalizers can compensate channel characteristic and reduce Intersymbol Interference without training sequence,so are used widely in many fields. First,float and fixed simulations had been done on the computer.The precisions of internal nodes in the equalizer had been chosed,and the relation between iterative step size,the length of filter ,the initialization of main tap weight and the performance of equlizer had been analyzed.Then,on the FPGA hardware plat,VerilogHDL code had been coded to implement blind equalizer of Bussgang family algorithm based on TOP-DOWN digital design methodology.Last,static timing analysis indicated that the result of implementation had been satisfied.The equalizer works well in the pratical system. The equalizer had been implemented on the Stratix family's FPGA manufactured by ALTERA, with the structure of transverse filter whose length is 17-tap.All operations are carried out in parallel hard architecture,and the whole system uses 19,000 LEs.For QPSK,16QAM,32QAM and 64QAM,the equalizer can work well and operate at 17Mhz. The code is reused and transplantable in good coding style.The paper proposed a good EDA design idea for digital signal processing ASIC design.The product of the paper will be used widely in digital communication system.