Suitable For High-speed Packet-switched Research And Implementation Of The Output Scheduling Policy

People bring forward more requirements on routers processing ability, switching capacity and throughput as the fast development of Internet to higher speed and broader band. Switch architecture and scheduling algorithm is the key points which limit the performance of router. For the lower demands of the memory speeds and the merit on more easily set up a system of greater capacity, parallel packet switch (PPS) became the hot research in the field of the T-Bit technology.On the demands of the PPS, the major functions of the output multiplexing stage are multiplexing the IP packets by the scheduling algorithm, which are from the multi-plane core switching structure. And deciding whether buffered the packets through the congestion states of the line card. For this output strategy, the thesis according to the requirements of 863 Terabit router project and basing on the analysis and comparison of scheduling algorithm in existence rigorously proofed the necessary and sufficient conditions of stable working for the bufferless and buffered PPS structure. The article also gives the necessary of the buffers in output stage and the lower bound. At last according to the queuing theory, the article discusses the server models.Based on the fore-mentioned analysis the article proposes one novel scheduling algorithm: MWDRR (Modified Weighted Deficit Round Robin) algorithms, which guarantee the fairness of the data link of the multi-plane core switching structure in the bandwidths. The engineering implementations are also given. With the care of the costs and the memory speeds along with bandwidths, this article expatiate a design which accessing bandwidth can reach 16.5Gbits/s only using normal DDR (Double Date Rate ) SDRAM. Synthesizing the algorithm and the design, the Schedule Module is able to schedule 12 IP packet queues operating at rate 2.5Gbps , Also assure buffering 250ms packets when the out ports speed are 10 Gbps. The key contributions and innovations of this thesis include: The problem of current scheduling scheme is pointed out and current scheduling algorithms are classified and compared with each other, and most studies in this field are summarized. Based upon reference switch and inventory theory thesis rigorously proofed the necessary and sufficient conditions of stable working for the bufferless and buffered PPS structure form the views of the fluid switches. And give the necessary of the buffers in output stage and its lower bound. According to the M/D/1 queuing models, conclude that the packets waiting time lying on thesevering rate provided by the system. A novel scheduling algorithms supporting variable-length packets and guaranteeing the fairness of data link, named as modified weighted deficit round robin (MWDRR), is proposed. The time complexity and fairness of MWDRR is analyzed, which is verified by the comparison results in the NS simulation. The engineering implementations are presented. Detailed analysis and design of key parts are also given. A design is expatiated which can satisfy the speed and capacity of the memory only using normal DDR (Double Date Rate) SDRAM. And implemented the DDR memory controller in FPGA. The output multiplexing stage module can schedule 12 IP packet queues operating at rate 2.5Gbps, Also assure buffering 250ms packets when the out ports speed are 10 Gbps.