A Pll 800mhz Cmos Clock Generator Design

Single frequency source is usually used as local oscillator in communication system and radar system, also as a reference clock in digital circuits, so it is a extensive-applied technique. There is a PLL(Phase Locked Loops) in system to get a high-stability low-noise high-frequency signal.A monolithic clock synthesis PLL, which is expected to be a reference 800MHz clock generator in accelerometer system, has been designed and characterized in this paper. The PLL consists of a crystal oscillator, a ring voltage-control-oscillator, a frequency divider, a phase/frequency detector, a charge pump and a loop filter.At the moment, most of RF chips and ultra high-speed circuits are based on technologies such as GaAs, Bipolar Si, BiCMOS and so on. With the development toward sub-micron and deep sub-micron technologies, CMOS will take more and more important role in the field of RF IC and have extremely wide market prospects,because its low cost and easy of implementation. Hence the frequency synthesizer has been designed in CSMC 0. 6μm CMOS technology.This paper introduces the design processes and final test results of above- mentioned circuit in detail according to the order of circuit theory, circuit design, circuit simulation. All circuit undergoes simulation, accord with the design requirement, the test results of the whole PLL circuit validate our specifications. It is suitable to apply to digital frequency measurement circuit in accelerometer system.