On-chip Fpga Design Of Network Routing Algorithms And Routing Nodes

Rapid development of technology brings chip design into billion-transistor field. It is predicted that at the end of this decade, it will allow more than one billion of transistor integrated on a single chip. As the number of cores of system chip increased, traditional SoC design methodology will not fit the billion-transistor field design requirement. At this time NOC, as a new solution, is presented. The scalable ability of NOC well meets the challenge of new design requirement. NOC gradually becomes a new communication structure besides traditional on-chip bus. In general, the complexity of NOC is characterized by two main factors, one is the network topology, and the other one is routing algorithm.This paper mainly introduced the Mesh topoplogy and Torus topology of NOC direct topology, and the popular routine techniques and algorithms. At the same time, a new dead-lock and live-lock free route algorithm to Torus topology is proposed. Moreover, we build the corresponding routing model for Mesh topology with XY routing algorithm and for Torus topology with self-designed routing algorithm, then simulate on OPNET and analyse the result.In order to valuate the feasibility and practicability of the NOC structure, we designed efficient hardware emulation and testing platform primarily consisted of DSP and FPGA. Furthermore, a five-component-microarchitecture model for router based on FPGA is proposed, verified and analysed, which lay the foundation for futhre research on NOC.