Research And Design Of Embedded System Development Platform For Ip Core Interface Layer

Since its high integrated performance, System on a chip (SoC), is regarded as the main replacement of integrated circuits, and already becomes inevitable' trend of microelectronic chips development. Because of the growing size of SoC design, implementing system capabilities in the form of IP Core becomes popular. However, how to guarantee the running of communication between different IP modules? And how to integrate IP Core more effeciently? All these problems still need to be solved. So, towards the IP Core interface compatibility of SoC Bus standard, this thesis, based on analyzing the interconnection of IP Cores, researches the software capsulation of IP Core Bus interface layer, and implements the IP Core interface layer of embedded system developing platform which is based on layers.In this thesis; the design method, flow, and environment of SoC based on IP demultiplexing is explained. While in order to improve the integration of IP Core on SoC, interconnection rules of IP Core and its standardization are researched. And the design necessarity of IP Core bus interface is analyzed. The design principle and internal structure of IP core bus interface are presented. The IP core interface layer is divided into specification transforming, block data processing and port priority arbitration. The IP Core bus interface is designed in two parts, including OCB-Initiator-Interface module, which transforms the IP Core request into OCB cycle request, and OCB-Target-Interface module, which transforms the OCB transporting into interface transporting. Finally, with USB 2.0 device controller IP Core and AHB bus. as instances, OCB-Target-Interface module is implemented. Writing of RTL code, designing and emulating are completed. The result of ModuleSim emulating coincides with demand expected, thus proving the feasibility of this design.