Based On The H.264/avc Video Decoder Vlsi Design And Research,

H.264/AVC is a new video coding standard with enhanced higher compression than H.263 and MPEG raised by ITU-T and MPEG orgnizations. This paper proposes an implementation of variable length decoder for H.264/AVC. While minimizing the use of clock cycles and hardware cost, the design is separated into several parts according to the specialty of the code stream. Bucket shift register is used to control circuit, and the first one detector is used in the process of decoding. In tabular decoding circuit, the design discards the traditional way which is the way of traversing search comparison. Instead, the table is devided into a number of sub-tables according to the feature of code streams. It makes tabular efficiency and circuit timing have great breakthroughs, especially in the total_coffe and no_zero level decode modules: the total_coffe module decode need only 2 cycles and the nozero level module decode need only 3 cycles, and the frequence of the modules is 220 Mhz.. By simulating with Quartus II 6.0, the results shows that its maximal working frequency is around 220 MHz and it could fulfill the required performance of H.264/AVC standard level 3.0.The main contents of this paper are as follows. Firstly, it is the presentation of the design and the verification of VLD decoder with VLSI, such as sythsis, fitter, STA, coding reference module and so on. Secondly, it is the introduction of video coding standard, the history of its development, and video codec theory, etc. Thirdly the protocal of H.264/AVC and the princinple about VLD CODEC is read and researched. Then it is the design of decode of VLD with Verilog. A new way of decoding the stream with faster speed and less cycle is used. At the same time we use IP reused design for tansplanting between different devices, so we use general FIFO interface with others. According the feature of code, a new way of looking for table is used when decoding cavlc. Concretely speaking, the original table is devided into many sub-tables. In this way the speed of circuit is higher and decode in less cycle. At the same time we optimised the archtecture of circuit to improve the speed of circuit. In the last part, the clock cycle of decoding is reduced, and the structure of decoder is optimized.