Improvement Of Etching Process Of 90 Nm DRAM Deep Groove Module

DRAM(Dynamic Random Access Memory)is formed with 1 transistor and 1 capacitor as a memory cell. DRAM is the most important memory device of computers until now. Follow Moore’s law, tremendous advances in process technology have dramatically reduced feature size, permitting ever higher levels of integration. These increases in integration have been accompanied by major improvements in component yield to ensure that overall process solutions remain cost-effective and competitive. With feature size of device dramatically reduced, the capacitor for every memory cell has no big difference. The biggest challenge is how to design the device with comparable capacitor in the case of dramatically reduced device size. Before the Mega Bit DRAM, the plane design is used; the plate of capacitor is limited by device area. After 4Mb DRAM was introduced, traditional plate capacitor can not support enough charge, then people began use 3D design for DRAM capacitor. The 3D cell has two possible structures: deep trench capacitor and stack capacitor.In this thesis, the process flow of 90nm deep trench DRAM capacitor is introduced. Some process issues were found in the mass production. To solve these problems, some FA (failure analysis) methods were used to find the root cause of these process issues. Also the design of experiment (DOE) is very helpful to find the way to improve the process and yield.In this thesis, different design of experiment schemes is used. In these schemes, the key factors of two levels were emphasized. The content include: (a) The brief introduction of the principle for key factors of tow level (b) Structure build up and experiment implement. Continuous response was focused on, at the same time; the scattered data was also discussed. DOE is an effective and configurable method to evaluate the effect of some response, the effect is from factors in the different levels. We used this kind of DOE method to analyze and improve the DRAM deep trench process.The investigation result indicates that the formation of the capacitors is the most important process of 90nm deep trench DRAM. The short after wet bottle etch which is induced by the large bottom dimension of deep trench. Also the small bottom dimension or the shallow depth will induce the lower capacitance. The key factors of the trench dimension are polymer deposition condition in the trench sidewall. The key of process stability is to improve the polymer deposition condition in the trench sidewall, while the polymer deposition condition is very sensitive to the temperature of lower electrode of the chamber and process time, which is liner in some process window. And we can also keep the process stable enough with the optimization of above parameters. We also found that the defect formed during the deep trench process while the coating of the material-- Y2O3, which have higher resistance to the plasma etch .was reduced. Based on the mass production experience, the happen ratio of the defect was increased after the lower electrode life time reached at about 160RF hours of the chamber or 3000hrs of the lower electrode. The creative work of this article is introduced a new method to monitor the deep trench profile. Monitoring the volume of the trench below 4um, which is called bottom void and the depth of the deep trench and so on, it can estimate the deep trench etch process is stable or not. The advantage of this new method is that it does not need damage the wafer compared with the standard method and with shortens response time and enough samples.The improvement of 90nm deep trench capacitor versus previous generation such as 110nm deep trench capacitor is in the cell layout and substrate, but the major advantage is to draw lessons from the stack capacitor formation, which also derivate related process such as Hemispherical Silicon Grains (HSG) deposition and recess and Single-Side Buried Strap (SSBS) etch process. The substrate of 90nm deep trench capacitor is rotated 45degree with checkerboard layout, which replaced merged isolation node trench (MINT) layout of 110nm deep trench capacitor and made it possible of deep trench wet bottle etch, HSG and SSBS process. The research result also indicates that, the top profile of deep trench will lead to Africa defect of SSBS process; the time mode etch in previous process will induced variation and bad uniformity of the depth of SSBS process. After collected mass production yield data, the yield loss induced by SSBS is about 15.3%.To solve such issues, we make the deep trench with bowing top profile to estimate the Africa defect and endpoint-catching to control SSBS process with deviation capacitor adjust to improve the uniformity and variation of the depth of overlap in SSBS process.