In Ic Design, Semiconductor Chip Yield Optimization

The semiconductor is being in an unprecedented transformation time, follow "Moore law" has brought physics and economical challenge emerges one after another incessantly, moreover these challenges often look like are unable to overcome. Now, the silicon part's characteristic size already was smaller than uses in silicon part which making lithograph's the light wave length. Once makes lithograph completes, the materials behavior and the electrical specification possibly enormous degree change chip performance and the reliability.These issues made a lot of problems in 130nm technology process. The chip yield is dropped dump quickly, but the cell numbers and the masking costs increases faster and faster. In this rich challenge significance's technical turning point, the product production process must be much slower than the anticipated speed. Will forecast 90nm and the 65nm production process future, the new light etching equipment, the mechanical stress and the material effect will cause the high yield rate realize with difficulty.In this article main research how to optimize the field rate in the IC design. Altogether divides into six chapters, chapter 1 is mainly the yield rate introduced simply, discuss with the reader to what is the classification, reason, the computational method and so on to have certain understanding, and has an approximate concept to the yield rate designing; The chapter 2 is to the yield rate design in some technical expressions and the specific concept introduction, including some basic definitions and some yield related component knowledge; The third chapter main concrete introduction the yield rateinfluence reasons, as well as IC Complier, the concrete step which optimizes the yield rate; The chapter 4 then specifically elaborated each step's function, has disbursed the yield rate design emphatically, also namely in various steps the yield rate design different rule and way; The chapter 5 has completed in electric circuit's power loss, succession, clock results and so on tree crab, chip area, wiring length, and carries on the concrete study with these results, elaborated has affected these results the possible factor, and has analyzed the reason which they produced.