Reconfigurable Architecture Based On Pipeline Reconfigurable Algorithm And The Aes Algorithm

Reconfigurable computing system has been developed based on general and special-purpose computer and ASICs, which combines the advantages of efficiency of ASICs and the flexibility of general-purpose computer. Many applications have shown to exhibit significant speed-ups using reconfigurable hardware, including: data encryption, signal processing and pattern recognition. Partial reconfiguration is a rising technology. When one module is being configured, others can still do their own job and don't to be affected. It can realize time sharing of system resource. Compared with early reconfigurable computing technology, partial reconfiguration can further improve resource utilization and system's performance.Currently, FPGA dynamically reconfigurable technology is based on the conventional SRAM FPGA on the starting platform, and the main successful applications often remain in the static system reconfiguration. Because of conventional SRAM FPGA, the chip logic function data overload required ms-around a few dozens of ms. At the time of data overload, reconfigurable dynamic continuity of the function of the system will be affected. In addition, the chip configuration time and chip area is proportional to the configuration. Because of its has to consume a large amount of time at the initial configuration on a huge data, making that The application of FPGA has been greatly hindered. So how to overcome such a reconfiguration and reduction of time slot, are dynamically reconfigurable systems achieve the bottleneck problem.For reconfigurable slot problem of the current dynamic reconfigurable technology, this article present and discuss a pipeline reconfigurable architecture prototype of a function-level design methodology, making use of pipelining and reconfigurable technology. The main contents is as follows.Firstly, this article introduces the status and significance of research of reconfigurable computing technology and analysis the existing problems. Then it brings forward an improved reconstruction of the structure of the pipeline at the existing reconfigurable pipelined structure.Secondly, this article discusses systemically the design method based on pipelined reconfigurable structure, and builds a mathematical model for the design method, and gives a general design method of pipelined reconfigurable structure.Finally, this method is tested by AES simulation. Some of reconfigurable systems is implemented in Xilinx Virtex-II Pro FPGA. It proved the advantages of the part of reconfigurable design through experimental results.